1. Field of the Invention
The present invention relates to a device with pillar-shaped components, and in particular, relates to an electronic device with pillar-shaped components.
2. Description of the Related Art
Recently, electronic devices such as cellular phones and digital cameras have been downsized, and therefore smaller semiconductor devices have been highly demanded for being mounted in such electronic devices. To meet such a demand, a wafer-level chip size packaging technology for forming a wafer-level chip size package (WL-CSP) has been developed. The WL-CSP is formed as a small package of the same size as a chip size. Furthermore, development of WL-CSPs each having an additional component mounted in a sealing resin has been also promoted.
For example, Japanese Patent Application Publication No. 2002-299496 (Patent Document 1) discloses a semiconductor device manufacturing method including a step of forming a post electrode composed of a stack of two copper (Cu) layers and a step of mounting a capacitor as an additional component sealed in a sealing resin. According to the method of Patent Document 1, as illustrated in a flowchart of FIG. 1, a post electrode is formed by the following steps (A) to (C):
A first Cu layer forming step including: forming a first resist film on a conductive film disposed on a semiconductor wafer (step S101); forming a hole by light-exposure and development (steps S102 and S103); forming the first Cu layer by plating (step S104); removing the first resist film (step S105); forming a temporary seal layer on the first Cu layer (step S106); and applying CMP to the first Cu layer and the temporary seal layer (step S107).
(B) A second Cu layer forming step including: forming a second resist film (step S108); forming a hole by light-exposure and development (steps S109 and S110); forming the second Cu layer by plating (step S111); removing the second resist film (step S112); forming a temporary seal layer on the second Cu layer (step S113); and applying CMP to the second Cu layer and the temporary seal layer (step S114).
(C) An electronic component mounting step including: removing the temporary seal layers (step S115); mounting a capacitor as an electronic component (step S116); forming an insulation layer (step S117); applying CMP to the capacitor and the insulation layer (step S118); and forming an electrode and a solder bump (step S119).
Furthermore, Japanese Patent Application Publication No. 2004-172163 (Patent Document 2) discloses a multilayered structure including a lower post electrode part (first post electrode part) and an upper post electrode part (second post electrode part) disposed on the lower post electrode part.
In the semiconductor device of Patent Document 1, a boundary position between the temporary seal layers as the first and second layers corresponds with a joint position between the first Cu layer and the second Cu layer. At the boundary position between the temporary seal layer as the first layer and the second temporary seal layer as the second layer, an undesirable ring-like projection part disposed at the boundary position between the temporary seal layers and extending in a circumferential direction is frequently formed on a lateral face part of the Cu post electrode composed of the first and second Cu layers.
Furthermore, in the semiconductor device of Patent Document 2, since a circumferential length of the second post electrode part is shorter than a circumferential length of the first post electrode part, a step (or a step-like part) is formed at a joint position between the first and second post electrode parts.
As described above, if a post electrode has a projection part or a step-like part disposed at the joint position between the layers (post electrode parts) made of copper whose mechanical strength is comparatively low, the projection part or the step-like part is subjected to internal stress caused by a substrate warpage or deformation. Therefore, the devices of Patent Documents 1 and 2 have a problem of a high frequency of occurrence of defective post electrodes, in which the post electrodes are fallen out or broken.